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Cache line aligned TT

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Let TT clusters (16*4=64 bytes) to hold on a singe cache line.
This avoids the need for the double prefetch.

Original patches by Lucas and Jean-Francois that has also tested
on his AMD FX:

BIG HASHTABLE

./stockfish bench 1024 1 18 > /dev/null

Before:
1437642 nps
1426519 nps
1438493 nps

After:
1474482 nps
1476375 nps
1475877 nps

SMALL HASHTABLE

./stockfish bench 128 1 18 > /dev/null

Before:
1435207 nps
1435586 nps
1433741 nps

After:
1479143 nps
1471042 nps
1472286 nps

No functional change.
This commit is contained in:
Marco Costalba
2013-04-26 18:45:54 +02:00
parent e508494a99
commit 083fe58124
4 changed files with 11 additions and 11 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
src/types.h
View File

@@ -56,10 +56,11 @@
# include <xmmintrin.h> // Intel and Microsoft header for _mm_prefetch()
# endif
#define CACHE_LINE_SIZE 64
#if defined(_MSC_VER) || defined(__INTEL_COMPILER)
# define CACHE_LINE_ALIGNMENT __declspec(align(64))
# define CACHE_LINE_ALIGNMENT __declspec(align(CACHE_LINE_SIZE))
#else
# define CACHE_LINE_ALIGNMENT __attribute__ ((aligned(64)))
# define CACHE_LINE_ALIGNMENT __attribute__ ((aligned(CACHE_LINE_SIZE)))
#endif
#if defined(_MSC_VER)