Cache line aligned TT

Let TT clusters (16*4=64 bytes) to hold on a singe cache line.
This avoids the need for the double prefetch.

Original patches by Lucas and Jean-Francois that has also tested
on his AMD FX:

BIG HASHTABLE

./stockfish bench 1024 1 18 > /dev/null

Before:
1437642 nps
1426519 nps
1438493 nps

After:
1474482 nps
1476375 nps
1475877 nps

SMALL HASHTABLE

./stockfish bench 128 1 18 > /dev/null

Before:
1435207 nps
1435586 nps
1433741 nps

After:
1479143 nps
1471042 nps
1472286 nps

No functional change.

src/tt.h

@@ -85,7 +85,7 @@ class TranspositionTable {
   static const unsigned ClusterSize = 4; // A cluster is 64 Bytes
 
 public:
- ~TranspositionTable() { delete [] table; }
+ ~TranspositionTable() { free(mem); }
   void new_search() { generation++; }
 
   TTEntry* probe(const Key key) const;
@@ -98,6 +98,7 @@ public:
 private:
   uint32_t hashMask;
   TTEntry* table;
+  void* mem;
   uint8_t generation; // Size must be not bigger then TTEntry::generation8
 };